Circuit design analysis of UHF passive RFID tags

Due to its high operating frequency, long read-write distance, no external power supply, and low manufacturing cost, UHF passive RFID tags have become one of the key directions of RFID research and may become mainstream products in the RFID field in the near future.

A complete UHF passive RFID tag consists of antenna and tag chip. Among them, the tag chip generally includes the following parts of the circuit: power recovery circuit, power supply voltage stabilization circuit, backscatter modulation circuit, demodulation circuit, clock extraction /generating circuit, starting signal generating circuit, reference source generating circuit, control unit, memory. The energy required for the passive RFID tag chip to work is entirely derived from the energy of the electromagnetic wave generated by the card reader. Therefore, the power recovery circuit needs to convert the UHF signal induced by the tag antenna into the DC voltage required for the chip to work. provide energy.

Since the electromagnetic environment in which RFID tags are located is very complex, the power of the input signal can vary hundreds or even thousands of times. Therefore, in order for the chip to work normally in different field strengths, a reliable power supply voltage stabilization circuit must be designed. . The modulation and demodulation circuit is the key circuit for the communication between the tag and the card reader. At present, most UHF RFID tags use ASK modulation. The control unit of an RFID tag is a digital circuit that processes instructions. In order to enable the digital circuit to reset correctly after the tag enters the field of the card reader, in response to the instructions of the card reader, a reliable startup signal generation circuit must be designed to provide a reset signal for the digital unit.

power recovery circuit

The power recovery circuit converts the UHF signal received by the RFID tag antenna into a DC voltage through rectification and boosting to provide energy for the chip to work. There are many possible circuit configurations for power recovery circuits. As shown in the figure are several power recovery circuits commonly used at present.

In these power recovery circuits, there is no optimal circuit structure, and each circuit has its own advantages and disadvantages. Under different load conditions, different input voltage conditions, different output voltage requirements and available process conditions, different circuits need to be selected to achieve optimal performance. The multi-stage diode voltage doubler circuit shown in Figure 2(a) generally uses Schottky barrier diodes. It has the advantages of high voltage doubling efficiency and small input signal amplitude, and is widely used. However, the common CMOS process of the general foundry does not provide Schottky barrier diodes, which will bring trouble to the designer in the selection of the process. Figure 2(b) replaces the Schottky diode with a PMOS tube connected in the form of a diode, which avoids special requirements on the process. The voltage doubling circuit with this structure needs a higher input signal amplitude, and has better voltage doubling efficiency when the output voltage is higher. Figure 2(c) is a traditional diode full-wave rectifier circuit. Compared with the Dickson voltage doubler circuit, the voltage doubler effect is better, but more diode elements are introduced, and the power conversion efficiency is generally slightly lower than the Dickson voltage doubler circuit. In addition, because its antenna input terminal is separated from the chip ground, it is a fully symmetrical structure with capacitor blocking DC when viewed from the antenna input terminal to the chip, which avoids the mutual influence between the chip ground and the antenna, and is suitable for use with symmetrical antennas (such as even pole antenna) connected. Figure 2(d) is the CMOS tube solution of the full-wave rectification circuit proposed by many literatures. In the case of limited technology, better power conversion efficiency can be obtained, and the requirements for the input signal amplitude are relatively low.

In the application of general passive UHF RFID tags, due to cost considerations, it is hoped that the chip circuit is suitable for the manufacture of ordinary CMOS technology. The requirement of long-distance reading and writing puts forward higher requirements on the power conversion efficiency of the power recovery circuit. For this reason, many designers use standard CMOS technology to realize Schottky barrier diodes, so that multi-stage Dickson voltage doubler circuit structure can be conveniently used to improve the performance of power conversion. Figure 3 is a schematic diagram of the structure of a Schottky diode manufactured by a common CMOS process. In the design, Schottky diodes can be produced without changing the process steps and mask generation rules, and only need to make some modifications on the layout.

The layout of several Schottky diodes designed under UMC 0.18um CMOS process. Their DC characteristic test curves are shown in Figure 5. It can be seen from the test results of the DC characteristics that the Schottky diode manufactured by the standard CMOS process has typical diode characteristics, and the turn-on voltage is only about 0.2V, which is very suitable for RFID tags.

Power regulator circuit

When the input signal amplitude is high, the power supply voltage stabilization circuit must be able to ensure that the output DC power supply voltage does not exceed the maximum voltage that the chip can withstand; at the same time, when the input signal is small, the power consumed by the voltage stabilization circuit should be as small as possible. To reduce the total power consumption of the chip.

From the point of view of the principle of voltage regulation, the structure of the voltage regulation circuit can be divided into two types: a parallel voltage regulation circuit and a series voltage regulation circuit.

In the RFID tag chip, there needs to be an energy storage capacitor with a large capacitance value to Store enough charge for the tag to receive the modulation signal, and the input energy can still be at the moment when the input energy is small (such as the moment when there is no carrier in OOK modulation). , to maintain the power supply voltage of the chip. If the input energy is too high and the power supply voltage rises to a certain level, the voltage sensor in the voltage stabilizing circuit will control the leakage source to release the excess charge on the energy storage capacitor, so as to achieve the purpose of voltage stabilization. Figure 7 is one of the parallel voltage regulator circuits. Three series connected diodes D1, D2, D3 and resistor R1 form a voltage sensor to control the gate voltage of the bleeder M1. When the power supply voltage exceeds the sum of the turn-on voltages of the three diodes, the gate voltage of M1 rises, M1 is turned on, and starts to discharge the energy storage capacitor C1.

The principle of another type of voltage stabilizing circuit is to use a series voltage stabilizing scheme. Its schematic diagram is shown in Figure 8. The reference voltage source is designed as a reference source independent of the supply voltage. The output power supply voltage is divided by the resistor and compared with the reference voltage, and the difference is amplified by the operational amplifier to control the gate potential of the M1 tube, so that the output voltage and the reference source basically maintain the same stable state.

This series voltage regulator circuit can output a more accurate power supply voltage, but because the M1 tube is connected in series between the unregulated power supply and the regulated power supply, when the load current is large, the voltage drop on the M1 tube will cause a higher voltage. power loss. Therefore, this circuit structure is generally applied to tag circuits with less power consumption.

Modulation and demodulation circuit

a. Demodulation circuit

For the sake of reducing the chip area and power consumption, most of the passive RFID tags currently adopt ASK modulation. For the ASK demodulation circuit of the tag chip, the commonly used demodulation method is the envelope detection method, as shown in FIG. 9 .

The voltage doubler circuit of the envelope detection part and the power recovery part is basically the same, but it is not necessary to provide a large load current. A leakage current source is connected in parallel at the final stage of the envelope detection circuit. When the input signal is modulated, the input energy decreases, and the leakage source reduces the envelope output voltage, so that the subsequent comparator circuit can judge the modulation signal. Due to the large range of energy variation of the input RF signal, the current of the leakage source must be dynamically adjusted to adapt to the changes of different field strengths in the near field and far field. For example, if the current of the leakage power supply is small, it can meet the needs of the comparator when the field strength is weak, but when the tag is in the near field with strong field strength, the leakage current will not be enough to make the detected signal If there is a large amplitude change, the post-stage comparator cannot work normally. To solve this problem, the leakage source structure as shown in Fig. 10 can be adopted.

When the input carrier is not modulated, the gate potential of the bleeder tube M1 is the same as the drain potential, forming a diode-connected NMOS tube, which clamps the envelope output near the threshold voltage of M1. The power consumed on M1 is balanced; when the input carrier is modulated, the input energy of the chip decreases, and at this time due to the action of the delay circuit R1 and C1, the gate potential of M1 remains at the original level, and M1 leaks The current released remains unchanged, which makes the amplitude of the envelope output signal decrease rapidly; similarly, after the carrier is restored, the delay of R1 and C1 makes the envelope output quickly return to the original high level. Using this circuit structure, and by choosing the size of R1, C1 and M1 reasonably, the demodulation needs under different field strengths can be met. There are also many options for the comparator circuit connected behind the envelope output, and the commonly used ones are hysteresis comparator and operational amplifier.

b. Modulation circuit

Passive UHF RFID tags generally adopt the backscattering modulation method, that is, by changing the input impedance of the chip to change the reflection coefficient between the chip and the antenna, so as to achieve the purpose of modulation. Generally, the impedance of the antenna and the input impedance of the chip are designed so that it is close to the power match when it is not modulated, and the reflection coefficient is increased when it is modulated. The commonly used backscattering method is to connect a capacitor with a switch in parallel between the two input ends of the antenna, as shown in Figure 11, the modulation signal determines whether the capacitor is connected to the input end of the chip by controlling the switch, thus changing the input impedance of the chip.

start signal generation circuit

The function of the power start reset signal generation circuit in the RFID tag is to provide a reset signal for the start work of the digital circuit after the power recovery is completed. Its design must consider the following issues: If the power supply voltage rises for too long, the high-level amplitude of the reset signal will be low, which cannot meet the needs of digital circuit reset; the start-up signal generation circuit is more sensitive to power fluctuations , it is possible to cause malfunction; the static power consumption must be as low as possible.

Usually, after the passive RFID tag enters the field, the time for the power supply voltage to rise is uncertain and may be very long. This requires the design of the startup signal generation circuit to generate the startup signal at the moment related to the power supply voltage. Figure 12 shows a common startup signal generation circuit.

Its basic principle is to use the branch composed of resistor R0 and NMOS transistor M1 to generate a relatively fixed voltage Va. When the power supply voltage vdd exceeds the threshold voltage of the NMOS transistor, the voltage of Va remains basically unchanged. As vdd continues to rise, when the power supply voltage reaches Va+|Vtp|, the PMOS transistor M0 is turned on to make Vb rise, and before that, Vb has been at a low level because M0 is cut off. The main problem with this circuit is the presence of static power dissipation. And because the threshold voltage of the MOS transistor varies greatly with the process under the CMOS process, it is easily affected by the process deviation. Therefore, using a pn junction diode to generate the start-up voltage will greatly reduce the uncertainty of the process, as shown in FIG. 13 .

When VDD rises to the turn-on voltage of the two pn junction diodes, the gate of the PMOS transistor M0 is equal to the power supply voltage, and the PMOS transistor is turned off. At this time, the voltage on the capacitor C1 is at a low level. When VDD rises above the threshold voltage of two diodes, M0 starts to conduct, while the gate voltage of M1 remains unchanged, the current flowing through M1 remains unchanged, and the voltage on capacitor C1 gradually increases. When it rises to the reverse phase After the device flips, a start signal is generated. Therefore, the time for this circuit to generate the start signal depends on whether the power supply voltage reaches the threshold voltage of the two diodes, which has high stability, and avoids the premature start signal of the general start circuit when the power supply voltage rises too slowly. The problem.

If the power supply voltage rises too fast, the gate capacitance of resistor R1 and M0 constitutes a low-pass delay circuit, which will make the gate voltage of M0 unable to quickly keep up with the change of the power supply voltage and remain at a low level. At this time M0 will charge the capacitor C1, causing the circuit not to work correctly. To solve this problem, a capacitor C5 is introduced. If the power supply voltage rises quickly, the coupling effect of the capacitor C5 can keep the gate potential of M0 consistent with the power supply voltage, avoiding the occurrence of the above-mentioned problems.

The problem of static power consumption still exists in this circuit, and the impact of static power consumption can be reduced by increasing the resistance value and selecting the size of the MOS tube reasonably. To completely solve the problem of static power consumption, it is necessary to design an additional feedback control circuit to shut down this part of the circuit after the start signal is generated. However, special attention needs to be paid to the instability caused by the introduction of feedback.

The design difficulty of passive UHF RFID chips revolves around how to increase the reading and writing distance of the chip and reduce the manufacturing cost of the tag. Therefore, improving the efficiency of the power recovery circuit, reducing the power consumption of the overall chip, and working reliably are still the main challenges in the design of RFID tag chips.